1. Field of the Invention
This invention relates to a thin-film semiconductor device which is applicable, for example, to an active matrix flat panel display and to a method for manufacturing the thin-film semiconductor device.
2. Description of the Related Art
The technique for semiconductor thin films is an important technology for forming semiconductor elements such as a thin-film transistor (TFT), a contact sensor, a photoelectric conversion device, etc. The thin-film transistor is a field-effect transistor of MOS (MIS) structure and is applied to a flat panel display such as a liquid crystal display device (for example, P. G. LeComber, W. E. Spear and A. Ghaith, “Amorphous-Silicon Field-Effect Device and Possible Application”, Electronics Letter, Vol. 15, No. 6, pp. 179-181, March 1979).
A liquid crystal display device is characterized in that it is generally thin in thickness, light in weight and low in power consumption, and that it is easy in displaying colors. In view of these characteristics, the liquid crystal display device is widely used as a personal computer or as a display for various kinds of mobile information terminals. When the liquid crystal display device is of active matrix type, the thin-film transistor is installed therein as a pixel switching element.
The active layer (carrier mobile layer) of the thin-film transistor is formed of a silicon semiconductor thin film for example. This silicon semiconductor thin film can be classified into amorphous silicon (a-Si) and polycrystalline silicon (non-monocrystalline silicon) having crystal phases. Although the polycrystalline silicon is mainly constituted by polycrystal silicon (Poly-Si), but microcrystal silicon (μc-Si) is also included in the definition of polycrystalline silicon. The materials for the semiconductor thin film include, other than silicon, for example SiGe, SiO, CdSe, Te, CdS, etc.
The carrier mobility of polycrystalline silicon is about 10-100 times as large as the carrier mobility of amorphous silicon. From this characteristic of polycrystalline silicon, it is evident that the polycrystalline silicon is very excellent for use as a semiconductor thin-film material for a switching element. In recent years, because of high-speed in operation, the thin-film transistor wherein polycrystalline silicon is used as an active layer has been noticed as a switching element which is capable of constituting various kinds of logic circuits such, for example, as a domino circuit and CMOS transmission gate. These logic circuits are needed for constituting the driving circuit of a liquid crystal display device or of an electroluminescence display device, a multiplexer, EPROM, EEPROM, CCD, RAM, etc.
Herein, the conventional representative process for forming a semiconductor thin film of polycrystalline silicon will be explained. In this process, an insulating substrate such as a glass substrate is prepared at first and then a silicon oxide film (SiO2) for example is formed as an undercoat layer (or a buffer layer) on the insulating substrate. Further, an amorphous silicon (a-Si) film is formed to a thickness of about 50-100 nm as a semiconductor thin film on this undercoat layer. Thereafter, the amorphous silicon film is subjected to dehydrogenation treatment for decreasing the hydrogen concentration in the amorphous silicon film. Then, by means of excimer laser crystallization method, etc., the fusion/recrystallization of the amorphous silicon film is performed. More specifically, excimer laser is irradiated to the amorphous silicon film, thereby converting the amorphous silicon into polycrystalline silicon.
In this manner, the thin-film transistor layer formed on a glass substrate is subjected to a fine working technique, a thin-film-forming technique, an impurity doping technique, a washing technique, a heat treatment technique, etc. which are now employed in the field of IC (LSI). These steps are repeated to create a desired device/circuit.
At present, a semiconductor thin film of polycrystalline silicon as described above is employed as an active layer of an n-channel or p-channel thin-film transistor. In this case, the field effect mobility (the mobility of electrons or holes by the electric field effect) of the thin-film transistor becomes about 100-150 cm2/Vsec in the case of the n-channel thin-film transistor and about 100 cm2/Vsec in the case of the p-channel thin-film transistor. By making use of the thin-film transistor as described above, driving circuits such as a signal line driving circuit and a scanning line driving circuit can be formed, together with a pixel switching element, on the same substrate, thus obtaining a driving circuit-integrated display device and thereby making it possible to reduce the manufacturing cost of the display device.
As described above, by promoting the refineness of the thin-film semiconductor device, it has been made possible to enhance the performance of device/circuit as well as the reliability of the system. However, there are many factors that deteriorate the reliability of thin-film semiconductor device in itself. These factors include a phenomenon called “hot carrier phenomenon” originating from the physical properties of device in addition to factors originating from the materials employed therein (such as disconnection due to the fatigue or corrosion of metal wirings, dielectric breakdown, the variation in characteristics of device due to contamination [by Na, etc.], etc.).
Namely, the electron that has been accelerated by the electric field in a channel is caused to impinge against the lattice of Si as the energy band of the electron is increased beyond the energy of band gap (1.1 eV), thereby generating an electron-hole pair (impact ionization). On this occasion, the electron is attracted by the gate voltage VG and enabled to jump into the gate oxide film even if the electron is not necessarily provided a high energy exceeding the potential barrier (about 3.1 eV) of Si—SiO2. Some of this electron is captured in this oxide film and permitted to remain therein as an electric charge. This not only causes the Vth of a transistor to shift toward the normal direction but also cause the mutual conductance gm to decrease. When the electric field inside the element is high, the electron existed in the channel is enabled to directly jump into the gate oxide film. The problem related to the reliabilities as described above is called “hot-carrier effect”, giving an important factor which obstructs the refining of the device.
This hot-carrier effect is caused by a high electric field. Accordingly, it is generally recognized that a method of providing an n-type (p-type) region of low dope concentration in the vicinity of the drain exhibiting a highest electric field to thereby alleviate the electric field is effective in suppressing the hot-carrier effect. A device which has been figured out to cope with this problem is a structure called “lightly doped drain (LDD)”, which is also effective in the p-type region.
This LDD is generally created as follows. First of all, by making use of a gate electrode as a mask, an n-type impurity ion and a p-type impurity ion are respectively implanted under a low doping condition {n−-(p−-layer)}. Subsequently, an SiO2 film is deposited all over the surface and then the entire surface of the SiO2 film is uniformly etched by means of oriented dry etching, thereby leaving a sidewall spacer consisting of the SiO2 film on the sidewall of gate. By making use of this spacer as a mask, the implantation of ion is performed under the condition where the doping concentration is made higher, thereby forming n+-layer (p+-layer). Since the impact ionization phenomenon depends strongly on the intensity of electric field, it is possible to improve the voltage resistance even if the alleviation in intensity of electric field is only 10%.
However, in the SiO2 etch-back process for forming the aforementioned LDD sidewall spacer, it is required to employ fine working techniques enabling very high uniformity. Although it is generally conceivable to employ a sidewall spacer having a width of about 200 nm in the Si-MOSFET of submicron rule, it is required, in order to form such a sidewall spacer, to form a sacrificial oxide film for forming a sidewall spacer having a width of about 500 nm. When the uniformity of etching is assumed to be ±10% for example, variability in thickness of ±50 nm may be caused to be transcribed to an underlying film. In the case of a gate oxide film having a 50-nm-thick underlying film, while the residual film thickness of the region where the etching rate distribution is the highest would become zero, the residual film thickness of the region where the etching rate distribution is the lowest would become 100 nm. Since it is generally conceivable that the gate oxide film deposited on the source/drain regions may be used as a through oxide film for the impurity doping to be subsequently performed, the variability of etching is required to be suppressed to at most ±10% or so to control the doping profile. When the underlying gate oxide film is set to 50 nm in thickness, the residual film thickness should be controlled so as to have a thickness of about 45-55 nm. Namely, unless the aforementioned etching variability of ±10% is reduced to ±1% in the aforementioned SiO2 etch-back process, it would be impossible to satisfactorily cope with the aforementioned requirement. It is no exaggeration to say that this reduced value can never be achieved by making use of the dry etching apparatuses which are now available in the market. As for alternative measures for solving this problem, it is conceivable to take some measures so as to prevent the variability of etching from being transcribed to the underlying film or to insert a buffering film which is capable of absorbing the variability of etching in the SiO2 etch-back process for forming the aforementioned sidewall spacer. In the case of the LSI device which is a predecessor of the refined device, the etch-back is performed in such a manner that the residual film of the underlying gate insulating film becomes zero, enabling the underlying Si active layer to expose and using the Si layer of the underlying Si substrate or of SOI substrate as a buffering layer. In this case however, it would become unavoidable to invite the dry etching damage in the etch-back process. If it is desired to recover from this damage, it is generally recognized to execute a heat treatment of around 1000° C. In the case of the LSI device, the recovery from this damage is assumed to be executed in a subsequent heat treatment step which is performed at a temperature of around 1000° C. In the case of TFT where glass is used as a substrate material however, it is difficult to employ a heat treatment of such a high temperature as described above. As far as the surface of glass substrate is concerned, the treatment temperature thereof is required to be confined to not higher than 600° C. in viewpoint of the heat resistance of the glass substrate. Therefore, it is now desired to develop an alternative technique which makes it possible to utilize even a low-temperature process.
The formation of the aforementioned sidewall spacer is now considered indispensable even in a future manufacturing process of a refined TFT where a high-melting-point metal silicide can be formed in a self-aligned manner in source/drain regions. Therefore, it is now considered indispensable to develop an etching control method which is needed for the formation of the sidewall and also to develop an etching control structure.
There are persistent expectations for the development of a method of forming a sidewall spacer which is indispensable in the creation of an LDD structure transistor or in the creation of a self-aligned silicide source/drain transistor, wherein the method can be carried out without giving any adverse influence to the device in terms of the working accuracy, in terms of stability enabling to carry out even in mass production and in terms of dry etching damage.
Since any method which requires a long time for the treatment cannot be a practical solution and since it is becoming increasingly difficult to adopt the batch treatment of substrates (a system to reduce the treatment time per sheet by performing the treatment of a plurality of sheets at the same time) due to the employment of a large size substrate, it is now desired, in view of the recent trend to adopt a sheet-to-sheet treatment, to figure out a solution enabling a low cost process in terms of manufacturing tact and apparatus cost.
First of all, the above problem was tackled in viewpoint of improving the uniformity of dry etching. As a result, it was found possible to expect the achievement of ±2% or so in uniformity of dry etching. However, it was found difficult to achieve the aforementioned level of ±1% or so in terms of the uniformity of dry etching. Even if it is possible to achieve such a low level in terms of the uniformity of dry etching, it cannot be constantly achieve such a low level in the process of mass production, thus rendering it as not a practical solution. Further, with respect to the method of utilizing the underlying Si layer as an etching stopper layer, it is no exaggeration to say that it is almost impossible to completely avoid the generation of damage in the dry etching process, so that to solve the problem, it is conceivably required to employ a method for recovering from the generated damage or to employ a method for removing a damaged layer. With regard to the former method, a heat treatment may be required for recovering from the damage and with regard to the latter method, it may be required to develop a device structure which is capable of removing the damaged layer. However, in the former method, it will be generally required to employ a temperature of as high as 1000° C. or so to achieve the recovery from the damage as described above, thus rendering the method conceivably unpractical in view of the heat resistance of the glass substrate. Even in the latter method, there is a problem that although the depth of damage is required to be confined to such a level that is allowable relative to the fluctuations of film thickness of the Si active layer, it has been already made clear that the thickness of the damaged layer is almost the same with or larger than the thickness of the Si active layer presently employed. In view of these facts, neither of methods is now found useful as a practical solution.